1. Field of the Invention
The present invention relates to a semiconductor memory and its manufacturing method; and more particularly to a semiconductor memory and its manufacturing method in which it is possible to manufacture high-integrated semiconductor memory in spite of its size of memory cells.
2. Description of Related Art
Conventionally, as for the semiconductor memory, there is the mask-ROM (Mask Programmed Read Only Memory). With reference to the mask-ROM, writing of data is carried out during the manufacturing process thereof. However, the mask-ROM is subjected to diffusion process of ion in which ion implantation is carried out in order to inject impurity into silicon substrate by the use of ion such as boron and so forth. In the diffusion process of the ion, the writing of data is carried out depending on this ion injection. Diffusion of the ion occurs in the lateral direction caused by this ion injection. Thus, there is malfunction that interference occurs between neighboring memory cells caused by the diffusion of the ion in the lateral direction. Specifically, the diffusion of the ion in the lateral direction causes threshold voltage to increase of the ON-bit memory cell neighboring the OFF-bit memory cell, thus, there is malfunction that ON-bit memory cell is rewritten into the OFF-bit memory cell caused by increase of the threshold voltage of the ON-bit memory cell. For that reason, the memory cell has a limit in connection with its miniaturization. For instance, it is difficult to form the microscopic memory cell not more than 0.20 xcexcm. Further, since the writing of data to the mask-ROM is carried out at the diffusion process, there is malfunction that many various intermediate off-the-shelf products according to content of the writing of data should be held by the time the manufacturing process ends.
Accordingly, OTP (One Time Programmable Read Only Memory) is employed as the measure for overcoming aforementioned malfunction. This OTP is PROM (Programmable Read Only Memory) to which writing data of only one time is capable of being carried out. The writing of data is carried out electrically. Therefore, interference between neighboring memory cells such as aforementioned mask-ROM can be inhibited. Since, it is only necessary to ensure reliability of writing of data of one time, it is possible to manufacture of the OTP cheaper than general semiconductor memory such as PROM, flash memory and so forth. Further, the OTP is capable of being written of the data after completion of the manufacturing process of the semiconductor memory not the process of diffusion of the ion (for instance in the test process), accordingly, inventory control becomes easy in comparison with the aforementioned mask-ROM.
Here, as for the OTP, which is explained on the basis of FIG. 4, FIG. 5 and FIG. 6.
FIG. 4 shows top plan typical view of memory cell portion of Virtual Ground Cell type large capacity NOR type OTP (semiconductor memory) 120 having impurity diffusion region 106 as a digit line. Further, FIG. 6 is a view illustrating a manufacturing process of this OTP 120 as well as a sectional view illustrating an arrow Axe2x80x94A of FIG. 4.
The OTP 120, as illustrated in FIG. 5, has a p-type silicon substrate 101 as single crystal silicon substrate, an impurity diffusion region 106 formed on the surface of this p-type silicon substrate 101, and a gate insulator 107 made of silicon oxide film that is formed on the surface of this p-type silicon substrate 101. Further, the OTP 120 has a floating gate electrode 109 made of polycrystalline silicon film formed on the gate insulator 107 extending between neighboring impurity diffusion regions 106, interelectrode insulating film 110 formed at unevenness portion (unevenness portion consisting of the gate insulator 107 and the floating gate electrode 109) of the p-type silicon substrate 101, control gate electrode 111 made of polycrystalline silicon film for embedding this unevenness portion, and tungsten silicide (Wsi) film 112 which is deposited on the control gate electrode 111.
Continuously, about manufacturing method of the OTP 120 is explained.
In the OTP 120, as illustrated in FIG. 6(a), firstly, buffer layer 102 made of oxide film is formed on the surface of the p-type silicon substrate 101 by thermal oxidation of the p-type silicon substrate 101, then, silicon nitride film 103 is deposited on the buffer layer 102 as insulating film. Then, the silicon nitride film 103 of a section that becomes impurity diffusion region 106 in the future is removed by photolithography and dry etching. After that, n-type injection layer 104 is formed in such a way that arsenic ion (As+) as n-type impurity is injected with the silicon nitride film 103 as mask material.
Continuously, as illustrated in FIG. 6(b), the buffer layer 102 and the silicon nitride film 103 are removed. The gate insulator 107 is formed on the surface of the p-type silicon substrate 101 in such a way as to carry out thermal oxidation of this p-type silicon substrate 101. Further, impurity diffusion region 106 is formed in such a way as to diffuse impurity of the n-type injection layer 104 during heat treatment carried out after such thermal oxidation. Furthermore, polycrystalline silicon film 108 is deposited on the gate insulator 107. Then, as illustrated in FIG. 6(c), floating gate electrode 109 made of the polycrystalline silicon film 108 is formed in such a way that the polycrystalline silicon film 108 on the impurity diffusion region 106 is subjected to patterning.
For instance, the floating gate electrode 109 is formed by the photolithography. On this occasion, the patterning is made to carry out while being employed approximately rectangular mask pattern for processing the floating gate electrode 109.
Subsequently, as illustrated in FIG. 6(d), an interelectrode insulating film 110 is formed on unevenness portion (unevenness portion consisting of the gate insulator 107 and the floating gate electrode 109) of the p-type silicon substrate 101. After that, the unevenness portion is embedded by the polycrystalline silicon film. Thus, the control gate electrode 111 made of the polycrystalline silicon film is formed. Further, tungsten silicide (WSi) film 112 which is deposited due to chemical vapor deposition method (CVD method) on the control gate electrode 111 is formed.
After that, as illustrated in FIG. 4, the OTP 120 is formed in such a way that patterning is made to carry out while leaving the floating gate electrode 109 that becomes word line 114, the interelectrode insulating film 110, the control gate electrode 111 and the tungsten silicide (WSi) film 112.
The OTP 120 indicated in the aforementioned conventional example has capacitance xe2x80x9cCsubxe2x80x9d between the p-type silicon substrate (except impurity diffusion region 106) and the floating gate electrode 109 as well as capacitance xe2x80x9cCgxe2x80x9d between the floating gate electrode 109 and the control gate electrode 111. Further, if one side of the impurity diffusion region 106 is taken to be drain region, while the other side is taken to be source region, the OTP 120 has capacitance xe2x80x9cCdxe2x80x9d between the drain region and the floating gate electrode 109, as well as capacitance xe2x80x9cCsxe2x80x9d between the source region and the floating gate electrode 109.
Ratio of the capacitance xe2x80x9cCgxe2x80x9d between the floating gate electrode 109 and the control gate electrode 111 relative to the total capacitance of all is called as capacitive coupling ratio xe2x80x9cCrxe2x80x9d, and this capacitive coupling ratio xe2x80x9cCrxe2x80x9d is indicated by formula (1):
Cr=Cg/(Cg+Csub+Cd+Cs)xe2x80x83xe2x80x83(1) 
One capacitance is mutual capacitance in the portion that the floating gate electrode 109 is extended over the impurity diffusion region 106 (capacitance xe2x80x9cCdxe2x80x9d between the drain region and the floating gate electrode 109 as well as capacitance xe2x80x9cCsxe2x80x9d between the source region and the floating gate electrode 109). The other capacitance is capacitance of opposite portion of the control gate electrode 111 to the side wall surface of the floating gate electrode 109. This capacitive coupling ratio xe2x80x9cCrxe2x80x9d takes aforementioned both capacitance to be main components. Further, the capacitive coupling ratio xe2x80x9cCrxe2x80x9d is made to increase by increasing these respective components, according to this strategy, voltage of writing data is capable of being suppressed in low voltage.
Extended portion of the floating gate electrode 109 described-above is a margin 121 illustrated in FIG. 6(c) that is required for mask matching when forming the floating gate electrode 109. Specifically, when the photolithography is carried out using approximately rectangular mask pattern, corner of the pattern of the photo-resist is rounded caused by occurrence of interference of light at the time of exposure at end of the rectangular portion. For that reason, if work (dry etching) of the floating gate electrode 109 is made to carry out while taking the pattern of this photo-resist to be the material of the mask, the floating gate electrode 109 itself becomes a rounded shape on its corner. When the rounded corner of this floating gate electrode 109 causes change of area of channel region of the memory cell, this malfunction is directly connected with change of characteristic of the memory cell itself.
For that reason, it is necessary that the margin 122 is made to ensure for separating the floating gate electrode 109 surely between neighboring memory cells, and that the rounded portion is not positioned on the channel region in such a way as to project the floating gate electrode 109 sufficiently on the impurity diffusion region 106. Further, it is necessary to consider a deviation of position for the exposure in the photolithography. On the basis of the aforementioned reason, the margin 121 that is designed enough widely is required.
On the other hand, it is necessary to minimize the margin 121 with reducing the size of the memory cell. However, with minimizing the margin 121, offset occurs between the impurity diffusion region 106 and the floating gate electrode 109. Namely, the extended portion disappears as the size of the memory cell is reduced. As a result, there is fear that the memory cell does not operate caused by no extended portion. Further, since the capacitive coupling ratio xe2x80x9cCrxe2x80x9d decreases as the size of the memory cell is reduced, voltage of the writing of data increases, thus operation margin of the memory cell decreases. Namely, as for the OTP 120 indicated in the above-described conventional example, it is difficult to realize that high integrated memory cell is made to obtain while reducing size of the memory cell, and that high integrated memory cell is made to obtain without changing the size of the memory cell.
The present invention has been made in consideration of the above mentioned problems. It is one object of the present invention is to provide a semiconductor memory and its manufacturing method in which it is possible to solve inconvenience included in the conventional example, particularly, it is possible to increase capacitive coupling ratio in spite of size of the memory cell, for that reason, it is possible to cause voltage of data-writing for applying to the memory cell to be lowered.
It is another object of the present invention to provide a semiconductor memory and its manufacturing method in which the memory cell can be made to operate effectively without changing size of the memory cell, or the memory cell can be made to operate effectively while reducing size of the memory cell.
The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region. Moreover, the floating gate electrode is extended to be provided on the surface of a side wall of the third insulating film.
By constituting the semiconductor memory in such a way described-above, specifically, the floating gate electrode can be made to form at the surface of the side wall (extended portion of the surface of the side wall of the impurity diffusion region) of the third insulating film, therefore, it is possible to form the semiconductor memory without taking into consideration offset between the impurity diffusion region and the floating gate electrode, that is feared at the time when reducing size of the memory cell of the semiconductor memory indicated in the conventional example. Namely, it is possible to form the semiconductor memory that operates effectively without taking into consideration decrease of the margin between the impurity diffusion region and the floating gate electrode with reducing size of the memory cell.
Also, film thickness of the third insulating film is made to form in such a way as to become thicker than total film thickness of the gate insulator and the floating gate electrode deposited on the gate insulator. Thus capacitance between the floating gate electrode and the control gate electrode can be made to increase, by thickening film thickness of the third insulating film, thus it is possible to increase the capacitive coupling ratio. Further, it is possible to increase the capacitive coupling ratio in spite of size of the memory cell.
A manufacturing method of a semiconductor memory according to the present invention indicates a manufacturing method in which an impurity diffusion region with a second conductive type that is opposite to a first conductive type is made to form on a surface of a semiconductor substrate with the first conductive type, in which a floating gate electrode is made to form on the semiconductor substrate via a gate insulator, and in which a control gate electrode is made to form on the floating gate electrode via an interelectrode insulating film.
Here, in the manufacturing method of the semiconductor memory, the manufacturing method comprises the steps of forming a fourth insulating film on a surface of the semiconductor substrate via a buffer layer consisting of an oxide film whose film thickness is thicker than that of the gate insulator, forming unevenness portion while carrying out patterning to the buffer layer and the fourth insulating film, before carrying out laying of a third insulating film to the unevenness portion, removing the buffer layer and the fourth insulating film, after smoothing the third insulating film until surface of the fourth insulating film being exposed, forming a polycrystalline silicon film at underside of concave portion of the semiconductor substrate via the gate insulator and forming a polycrystalline silicon film on the third insulating film, and forming a floating gate electrode while removing the polycrystalline silicon film existing on an upper surface of the third insulating film.
For that reason, it is possible to form the floating gate electrode in such a manner as to form it in self-adjustable method at the surface of the side wall of the third insulating film (extended portion of the surface of the side wall of impurity diffusion region). Further, it is possible to manufacture the memory cell without consideration of margin between the floating gate electrode and the impurity diffusion region like the conventional example.
Further, total film thickness of the buffer layer and the fourth insulating film is formed thicker than total film thickness of the gate insulator and the polycrystalline silicon film existing on the gate insulator. Thereby, as described above, film thickness of the third insulating film can be made to form in such a way as to become thicker than total film thickness of the gate insulator and the floating gate electrode deposited on the gate insulator.
Here, when the third insulating film is formed with the High Density Plasma CVD method, the third insulating film is capable of being laid effectively on the unevenness portion of the silicon substrate. For instance, even though interval of the unevenness portion becomes narrow at the time realizing high-integrated memory cell or reducing size of the memory cell, it is possible to carry out laying of the third insulating film effectively by the use of the High Density Plasma CVD method with high characteristic for embedding to narrow gap.
Also, the semiconductor substrate is formed with single crystal silicon, the control gate electrode is formed with polycrystalline silicon, silicon oxide films are formed as the gate insulator and the third insulating film, silicone nitride film is formed as the fourth insulating film, and three layer structure insulating film consisting of a first silicon oxide film, a silicon nitride film and a second silicon oxide film is made to carry out as the interelectrode insulating film.